1. Field of the Invention
The present invention relates to a semiconductor memory having a redundancy circuit for relieving defects in memory cell regions. In particular, the present invention relates to a nonvolatile semiconductor memory having a redundancy circuit.
2. Description of the Related Art
In general, semiconductor memories are broadly classified into volatile semiconductor memories such as a DRAM (Dynamic Random Access Memory) which require power to hold data, and nonvolatile semiconductor memories such as a flash memory/EEPROM (Electrical Erasable Programmable Read Only Memory) which require no power to hold data. The performance of a semiconductor memory is often expressed in memory capacity, access speed, and power consumption.
DRAMs are mainly used for computer""s main storage as large-capacity high-speed semiconductor memories. Because of being volatile, however, DRAMs require refresh operations to hold data, and thus are high in power consumption.
Flash memories/EEPROMs are mainly used for file systems, memory cards, portable equipment, and the like as large-capacity, low-power-consumption nonvolatile semiconductor memories. Flash memories/EEPROMs, however, require extremely longer time for data write.
Meanwhile, ferroelectric memories having memory cells composed of ferroelectric capacitors have been recently developed as semiconductor memories that combine the advantages of DRAMs and flash memories/EEPROMs. Ferroelectric memories can hold data even without power supply, by utilizing residual polarization that remains even after the voltages applied to their ferroelectric capacitors are removed.
Ferroelectric memories are increasing in memory capacity year after year, and their substitution for flash memories is under consideration. The rise in memory capacity tends to increase chip size. On this account, defect-relieving technologies (redundancy circuit technologies) for ferroelectric memories have been studied recently. Among known redundancy circuit technologies for ferroelectric memories is one disclosed in Japanese Unexamined Patent Application Publication No. 2000-215687, for example.
The ferroelectric memory disclosed in this publication contains ordinary memory cells, redundancy memory cells, and memory cells for redundancy files for retaining the column addresses of memory cells to be relieved as replacement information. These memory cells, redundancy memory cells, and memory cells for redundancy files are connected to common word lines. That is, in read operations and write operations, the memory cells, redundancy memory cells, and memory cells for redundancy files are simultaneously selected in accordance with the activation of the word lines. Each single redundancy memory cell is formed for, e.g., eight ordinary memory cells.
The ferroelectric memory has a logic circuit for decoding replacement information (defect addresses) read from the memory cells for redundancy files to generate decoding signals corresponding to each column address, and a logic circuit for generating the OR logic of these decoding signals. Column switches for the memory cells are deselected in response to any of the decoding signals. Column switches for the redundancy memory cells are selected in response to the OR logic of the decoding signals. That is, in response to the replacement information, access to defective memory cells is disabled and access to redundancy memory cells is enabled to relieve the defective memory cells.
FIG. 1 shows an overview of a ferroelectric memory having a redundancy circuit of this type.
In the diagram, the ferroelectric memory has a plurality of memory blocks MB. The memory blocks MB each have a word driver 10, a plate driver 12, a column control circuit 14, a memory cell region MCR, a redundancy memory cell region RCR, and a redundancy information region DCR.
The word driver 10 supplies a voltage to a predetermined word line WL according to a row address. The plate driver 12 supplies a voltage to a predetermined plate line PL according to the row address. The column control circuit 14 outputs column selecting signals CL and a redundancy column select signal RL to the memory cell region MCR and the redundancy memory cell region RCR, respectively, in accordance with a column address as well as relief information (relief address information and the like) output from the redundancy information region DCR. The activation of the column selecting signals CL turns on the column switches (not shown) in the memory cell region MCR. The activation of the redundancy column selecting signal RCL turns on the redundancy column switches (not shown) in the redundancy memory cell region RCR.
The memory cell region MCR is composed of memory cells MC to be used in normal operations. The redundancy memory cell region RCR is composed of memory cells MC for relieving defective memory cells. The redundancy information region DCR is composed of memory cells MC for indicating the locations of the defective memory cells. The memory cells MC in the memory cell region MCR, the redundancy memory cell region RCR, and the redundancy information region DCR are connected to common word lines WL and plate lines PL In read operations and write operations, memory cells in the memory cell region MCR, the redundancy memory cell region RCR, and the redundancy information region DCR are simultaneously selected in accordance with the activation of a word line WL and a plate line PL. In other words, memory cells MC that are activated between a word line WL and a plate line PL become accessible.
For example, if a word line WL and a plate line PL are activated to read relief information showing relief from a memory cell MC in the redundancy information region DCR, the column select signals CL are inactivated and the redundancy select signal RCL is activated. The inactivation of the column selecting signals CL turns off the column switches to disable the access to the defective memory cells MC in the memory cell region MCR (marked with crosses in the diagram). The activation of the redundancy column selecting signal CL turns on the redundancy column switches to enable the access to the memory cells MC in the redundancy memory cell region RCR (marked with circles in the diagram). That is, the defective memory cells MC are replaced with the normal memory cells MC to relieve the memory cells MC.
In the ferroelectric memory cell disclosed in the above-mentioned publication, the memory cells, redundancy memory cells, and memory cells for redundancy files are selected at the same time. Therefore, it is of importance to the high speed execution of read/write operations how to operate the column switches quickly in response to replacement information (column address). In the ferroelectric memory described above, however, the column switches for the redundancy memory cells are selected in accordance with the OR logic of the decoding signals which select the column switches for the ordinary memory cells. Accordingly, there has been a problem that the column switches for the redundancy memory cells delay in operation, with slower access time particularly during redundancy operations. The access time of a semiconductor memory is determined by the access time of the slowest memory cells. As a result, the access time of the redundancy memory cells makes the actual access time of the chip. Besides, there has been a problem that a rise in the circuit scale of the redundancy circuit can increase the chip size.
In each memory block MB of the ferroelectric memory shown in FIG. 1, the memory cell region MCR, the redundancy memory cell region RCR, and the redundancy information region DCR are successively arranged next to the word driver 10 and the plate driver 12. That is, the redundancy information region DCR is placed far from the word driver 10 and the plate driver 12.
Word lines WL and plate lines PL typically have parasitic resistance and parasitic capacitance. Thus, the farther from the word driver 10 and the plate driver 12 the memory cells MC are, the longer it takes until signals (voltages) are transmitted thereto. The memory cells MC of the redundancy information region DCR, farthest from the word driver 10 and the plate driver 12, are selected later than the other memory cells MC.
Due to the late selection of the memory cells MC in the redundancy information region DCR, the relief information is output from the redundancy information region DCR with a delay. Consequently, there has been a problem that the memory cells MC in the memory cell region MCR and the redundancy memory cell region RCR cannot be read/written quickly even though these memory cells MC are already selected. That is, there has been a problem of yet slower access time.
Since the memory cells MC in the memory cell region MCR, the redundancy memory cell region RCR, and the redundancy information region DCR are simultaneously selected by the word lines WL and plate lines PL, it is of importance to the high speed execution of read/write operations how to operate the column control circuit 14 quickly in response to the relief information (column address).
An object of the present invention is to reduce the access time of a semiconductor memory. More particularly, the object is to prevent a delay in access time when operating a redundancy circuit in the semiconductor memory.
Another object of the present invention is to reduce a semiconductor circuit in access time and in chip size as well.
Still another object of the present invention is to reduce the circuit scale of a redundancy circuit, thereby decreasing the chip size of the semiconductor memory.
According to one of the aspects of the present invention, a semiconductor memory includes a memory cell region, a redundancy memory cell region, a redundancy information region, and a word driver for supplying a word line selecting signal to word lines. The redundancy information region is arranged closer to the word driver with respect to the memory cell region and the redundancy memory cell region. The memory cell region has memory cells to be used in normal operations. The redundancy memory cell region has memory cells for relieving defective memory cells in the memory cell region. The redundancy information region has memory cells for retaining relief information indicating the locations of the defective memory cells. The memory cells in the memory cell region, the redundancy memory cell region, and the redundancy information region are connected to common word lines. In this semiconductor memory, a predetermined word line selecting signal (word line) is activated in accordance with the supply of an address or the like, thereby selecting predetermined memory cells in the memory cell region. Here, predetermined memory cells in the redundancy memory cell region and redundancy information region which are connected to the same word line are also selected. Word lines contain wiring resistance and load capacitance. Therefore, the closer to the word driver the memory cells are, the earlier the word line selecting signal is transmitted thereto. Since the redundancy information region is arranged closer to the word driver, the memory cells in the redundancy information region operate earlier than the memory cells in the memory cell region and the redundancy memory cell region.
When the memory cell region is in operation, the defective memory cells are deselected in accordance with the relief information held in the redundancy information region corresponding to these memory cells. The memory cells in the redundancy memory cell region which relieve the defective memory cells are selected in accordance with the relief information held in the redundancy information region corresponding to the defective memory cells. Since the memory cells in the redundancy information region that retain the relief information start operation earlier, a relief/no-relief judgment can be made earlier. As a result, the access time can be reduced in either case, relieving or not relieving memory cells.
According to another aspect of the present invention, a semiconductor memory includes a memory cell region, a redundancy memory cell region, a redundancy information region, and a plate driver for supplying a plate voltage to plate lines. The redundancy information region is arranged closer to the plate driver with respect to the memory cell region and the redundancy memory cell region. The memory cell region has memory cells to be used in normal operations. The redundancy memory cell region has memory cells for relieving defective memory cells in the memory cell region. The redundancy information region has memory cells for retaining relief information indicating the locations of the defective memory cells. The memory cells in the memory cell region, the redundancy memory cell region, and the redundancy information region are connected to common plate lines. In this semiconductor memory, a predetermined plate line is activated in accordance with the supply of an address or the like, thereby selecting predetermined memory cells in the memory cell region. Here, predetermined memory cells in the redundancy memory cell region and redundancy information region which are connected to the same plate line are also selected. Plate lines contain wiring resistance and load capacitance. Therefore, the closer to the plate driver the memory cells are, the earlier the plate voltages supplied to the plate lines are transmitted thereto. Since the redundancy information region is arranged closer to the plate driver, the memory cells in the redundancy information region operate earlier than the memory cells in the memory cell region and the redundancy memory cell region.
Consequently, as mentioned above, the memory cells in the redundancy information region which retain relief information start operation earlier, thereby allowing an earlier relief/no-relief judgment. This can reduce the access time in either case, relieving or not relieving memory cells.
According to another aspect of the present invention, a semiconductor memory includes a memory cell region, a redundancy memory cell region, and a redundancy information region. The semiconductor memory also has at least either a word driver for supplying a word line selecting signal to word lines or a plate driver for supplying a plate voltage to plate lines.
Each of these components is configured as in the semiconductor memories described above. Therefore, as mentioned above, the access time can be reduced in either case, relieving or not relieving memory cells.
According to another aspect of the present invention, the memory cell region and the redundancy memory cell region have a column switch and a redundancy column switch for inputting and outputting data to read from and/or write to the memory cells in these regions, respectively. When the relief information read from a memory cell in the redundancy information region shows xe2x80x9cno relief,xe2x80x9d the column switch is activated to read data from and/or write data to memory cells in the memory cell region. When the relief information shows xe2x80x9crelief,xe2x80x9d the redundancy column switch is activated to read data from and/or write data to memory cells in the redundancy memory cell region. Since the operations of the column switch and redundancy column switch are started earlier, the access time is reduced.
According to another aspect of the present invention, the memory cells in the redundancy information region consist of nonvolatile memory cells. Therefore, the relief information indicating the locations of the defective memory cells can be retained even without power supply. The nonvolatile memory cells have, for example, ferroelectric capacitors for retaining written data.
The memory cell region and the redundancy memory cell region are composed of the nonvolatile memory cells having the same configuration as those composing the redundancy information region. This makes it possible for these memory cells to be designed according to the same layout rule and fabricated by the same semiconductor processes. As a result, the chip size can be reduced. The reduced chip size combines with the facilitated fabrication processes to achieve reduction in fabrication costs.
According to another aspect of the present invention, a semiconductor memory includes a plurality of memory regions each composed of a memory cell region, a redundancy memory cell region, and a redundancy information region, and a plurality of plate drivers individually arranged next to the memory regions. In general, word lines are connected to ferroelectric capacitors through the gates of transfer transistors in memory cells. Plate lines are connected directly to the ferroelectric capacitors. Since the loads connected to the plate lines include the ferroelectric capacitances and the like of the memory cells, they are greater than the loads connected to the word lines. Forming a plurality of plate drivers corresponding to the plurality of memory regions can reduce the lengths of the plate lines, thereby decreasing the loads of the plate lines. As a result, the effect of the loads of the plate lines on access time can be minimized with reduction in access time.
According to another aspect of the present invention, a semiconductor memory includes a plurality of memory regions, as well as a plurality of redundancy memory regions, a plurality of redundancy address regions, and a plurality of redundancy flag regions respectively corresponding to the memory regions. The memory regions contain a plurality of memory cells each. The redundancy memory regions have redundancy memory cells for relieving a defect in any of the memory cells in the memory regions. That is, each single redundancy memory cell is formed per plurality of memory cells. The redundancy address regions hold, as address information, second addresses designating the defective memory cells. The redundancy flag regions hold relief information indicating the use of the redundancy memory regions.
In this semiconductor memory, a first address and a second address are supplied to the semiconductor memory. Any of the plurality of memory regions is selected in accordance with the first address. Then, any of the plurality of memory cells arranged in each memory region is selected in accordance with the second address. The memory region, the redundancy memory region, the redundancy address region, and the redundancy flag region corresponding to the same first address are activated at the same time.
When the memory region is in operation, the defective memory cell is deselected in accordance with the address information held in the redundancy address region corresponding to this memory cell. Specifically, the region containing the defective memory cell is identified by decoding a signal that is read as the address information. The redundancy memory cell to relieve the defective memory cell is selected in accordance with the relief information held in the redundancy flag region corresponding to the defective memory cell. That is, redundancy memory cells are directly selected in accordance with relief information, without using address information. Since the number of gates of circuits to be involved from the selection of a word line to the selection of a redundancy memory cell can be reduced, it is possible to reduce the time that elapses before the redundancy memory cell is selected after the selection of the word line. This makes it possible to avoid a delay in access time when relieving memory cells.
According to another aspect of the present invention, the redundancy address regions and the redundancy flag regions are composed of nonvolatile memory cells. Therefore, the address information and relief information can be retained even without power supply. The memory cells have, for example, ferroelectric capacitors for retaining written data.
According to another aspect of the present invention, the memory cells in the redundancy flag regions are each connected to one of complementary bit lines (true bit line and bar bit line) for transmitting the relief information.
For example, in writing a logical value of 1 to the memory cells, high level is transmitted to the true bit line and low level is transmitted to the bar bit line. Relief information of high level is written to the memory cells that are connected to the true bit line (true memory cells). Relief information of low level is written to the memory cells that are connected to the bar bit line (bar memory cells). Likewise, in writing a logical value of 0 to the memory cells, relief information of low level is written to the true memory cells and relief information of high level is written to the bar memory cells.
Hereinafter, description will be given of the case where the memory cells are written with a logical value of 1. To read the relief information (high level) retained in the true memory cells to the true bit line, a reference voltage is supplied to the bar bit line. A potential difference between the true bit line (high level) and the bar bit line is amplified by a sense amplifier and the like, so that the true bit line is brought to high level and the bar bit line is brought to low level. Similarly, to read the relief information (low level) retained in the bar memory cells to the bar bit line, the reference voltage is supplied to the true bit line. A potential difference between the true bit line and the bar bit line (low level) is amplified by sense amplifiers and the like, so that the true bit line is brought to high level and the bar bit line is to low level. That is, the same levels are read out to the complementary bit lines, regardless of whether the information is read out from true memory cells or bar memory cells. The relief information held in the true memory cells and the bar memory cells can be read out by using either the true bit line, or the bar bit line alone. As a result, the redundancy circuit can be formed with a simple configuration, which allows reduction in the chip size of the semiconductor memory.
According to another aspect of the present invention, the memory cells and the redundancy memory cells consist of the nonvolatile memory cells having the same configuration as those composing the redundancy memory regions and the redundancy flag regions. On this account, the memory cells in the memory regions, the redundancy memory regions, the redundancy address regions, and the redundancy flag regions can be designed on the same layout rule and fabricated by the same semiconductor processes. This allows reduction in chip size. The reduced chip size combines with the facilitated fabrication processes to achieve reduction in fabrication costs.
According to another aspect of the present invention, the nonvolatile memory cells in the memory regions, the redundancy memory regions, the redundancy address regions, and the redundancy flag regions are selected by common word lines to be activated in accordance with the first address. The use of the common word lines makes it possible to reduce the total number of word lines to be laid over the entire regions. That is, the individual regions can be minimized in layout size, with reduction in chip size.
According to another aspect of the present invention, the redundancy address regions hold binary data of the second address as the address information. Therefore, the redundancy address regions can be configured to be smaller in size.